1. Field of the Invention
The present invention relates to a method and apparatus for designing a semiconductor integrated circuit device. In particular, it relates to a method and apparatus for arranging transistors or cells, that is, a transistor assembly having a logic function in consideration of a voltage drop value.
2. Description of the Related Art
Recently, a manufacturing process of semiconductor has rapidly been finer, and the scale of a transistor has significantly been increased. Accordingly, also power consumption of a semiconductor chip unit is rapidly increased. Therefore, at the present time, it is desired to suppress the increase in power consumption as much as possible by, for example, reducing supply voltage (operating voltage), etc.
In this way, by reducing a voltage supply in order to suppress the increase in power consumption, a value of electric current is increased. Then, with such an increase in the value of electric current, the circuit operation may be adversely affected. In order to cope with such a problem accompanying a voltage drop in a semiconductor chip, for example, JP 11 (1999)-45979A discloses a method for reducing a voltage drop. JP 2000-194732A discloses a method for exactly analyzing a voltage drop value. On the other hand, JP2000-163460A discloses a method for reducing a voltage drop itself while analyzing a voltage drop.
In the above-mentioned method for analyzing and reducing a voltage drop, an analysis of power consumption and the voltage drop value is conducted with respect to transistors or cells which are substantially or perfectly arranged. Then, by verifying the timing with the use of a transistor delay corresponding to the voltage drop value, the occurrence of an operation defect after manufacturing is suppressed or the suitable power supply wiring is reinforced in order to reduce the rate of the voltage drop.
However, it is not possible to avoid the occurrence of a voltage drop to some extent and, in general, a certain amount of a voltage drop, which may be generated, is included in the design as a design margin of the entire circuit. That is, when it is estimated that the voltage drop of 10% occurs, a circuit design with higher speed by 10% than the usual specification is carried out. Thus, even if a voltage drop occurs, the operation speed in accordance with specification can be secured.
Since such a designing method is employed, based on the timing verification on a circuit, cells belonging to a path having a relatively large timing margin have the same power supply reinforcement as cells belonging to the critical path. This causes an unnecessary increase in the area of the chip.
Furthermore, in carrying out a logic synthesis, in general, since the process such as a logic synthesis is carried out assuming an ideal clock, even if a path from a clock source to each flip-flop is an isometry wiring or isovolume wiring, delay distribution occurs due to the influence of a voltage drop. Therefore, the clock delay distribution (skew) margin to be included at the time of synthesis is necessary to be included in a significant margin design by considering the most of a voltage drop distribution in addition to a functional wiring length of an arranged wiring tool and a wiring capacitance control distribution.
Then, even if such a timing margin is reduced and the timing optimization by real dock delay information is executed after the wiring is finished, since the configuration of the circuit is changed and thus the voltage drop value differs from that before the timing optimization is carried out, the timing optimization process may not be converged.
Furthermore, in a test circuit (scan circuit) for detecting a failure place in a circuit, since in general, scan chain assuming an ideal clock is carried out, a voltage drop may be maximum at the time of scan operation, and thus a failure detection test cannot be carried out because of the clock skew by the influence of the voltage drop